View CY7C1347B-133AC_2511931.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

128k x 36 synchronous-pipelined cache ram cy7c1347b cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 march 11, 2001 1cy7c1347 features ? supports 100-mhz bus for pentium ? ? ? ? and powerpc? operations with zero wait states fully registered inputs and outputs for pipelined oper- ation 128k by 36 common i/o architecture 3.3v core power supply 2.5v/3.3v i/o operation fast clock-to-output times ? 3.5 ns (for 166-mhz device) ? 4.0 ns (for 133-mhz device) ? 5.5 ns (for 100-mhz device) user-selectable burst counter supporting intel ? ? ? ? pen- tium interleaved or linear burst sequences separate processor and controller address strobes synchronous self-timed writes asynchronous output enable jedec-standard 100 tqfp pinout ?zz? sleep mode option and stop clock option available in industrial and commercial temperature ranges functional description the cy7c1347b is a 3.3v, 128k by 36 synchronous-pipelined cache sram designed to support zero-wait-state secondary cache with minimal glue logic. the cy7c1347b i/o pins can operate at either the 2.5v or the 3.3v level, the i/o pins are 3.3v tolerant when v ddq = 2.5v. all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. max- imum access delay from the clock rise is 3.5 ns (166-mhz device). the cy7c1347b supports either the interleaved burst se- quence used by the intel pentium processor or a linear burst sequence used by processors such as the powerpc. the burst sequence is selected through the mode pin. accesses can be initiated by asserting either the processor address strobe (adsp ) or the controller address strobe (adsc ) at clock rise. address advancement through the burst sequence is con- trolled by the adv input. a 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualified with the four byte write select (bw [3:0] ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are conducted with on-chip synchronous self-timed write cir- cuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank se- lection and output three-state control. in order to provide prop- er data during depth expansion, oe is masked during the first clock of a read cycle when emerging from a deselected state. pentium and intel are registered trademarks of intel corporation. powerpc is a trademark of ibm corporation. clk adv adsc a [16:0] gw bwe bw 3 bw 2 bw 1 bw 0 ce 1 ce 3 ce 2 oe zz burst counter address register output registers input registers 128kx36 memory array clk clk q 0 q 1 q d ce ce clr sleep control 36 36 17 15 15 17 (a [1;0] ) 2 mode adsp logic block diagram dq [31:0] dp [3:0] dq[31:24], dp[3] bytewrite registers dq dq[23:16], dp[2] bytewrite registers dq dq dq[15:8], dp[1] bytewrite registers dq[7:0], dp[0] bytewrite registers dq enable ce register dq enable delay register dq
cy7c1347b 2 pin configurations a 5 a 4 a 3 a 2 a 1 a 0 nc nc v ss v dd nc nc a 10 a 11 a 12 a 13 a 14 a 15 a 16 dp 1 dq 15 dq 14 v ddq v ssq dq 13 dq 12 dq 11 dq 10 v ssq v ddq dq 9 dq 8 v ss nc v dd zz dq 7 dq 6 v ddq v ssq dq 5 dq 4 dq 3 dq 2 v ssq v ddq dq 1 dq 0 dp 0 dp 2 dq 16 dq 17 v ddq v ssq dq 18 dq 19 dq 20 dq 21 v ssq v ddq dq 22 dq 23 nc v dd nc v ss dq 24 dq 25 v ddq v ssq dq 26 dq 27 dq 28 dq 29 v ssq v ddq dq 30 dq 31 dp 3 a6 a7 ce 1 ce 2 bw 3 bw 2 bw 1 bw 0 ce 3 v dd v ss clk gw bwe oe adsc adsp adv a 8 a 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode byte0 byte1 byte3 byte2 100-pin tqfp cy7c1347b
cy7c1347b 3 pin configurations (continued) 2 34567 1 a b c d e f g h j k l m n p r t u v ddq nc nc dqp c dq c dq d dq c dq d aa aa adsp v ddq ce 2 a dq c v ddq dq c v ddq v ddq v ddq dq d dq d nc nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc v dd nc nc nc nc nc nc nc v ddq v ddq v ddq aaa a ce 3 a a a a a a a0 a1 dq a dq c dq a dq a dq a dq b dq b dq b dq b dq b dq b dq b dq a dq a dq a dq a dq b v dd dq c dq c dq c v dd dq d dq d dq d dq d adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss dqp a mode dqp d dqp b bw b bw c nc v dd nc bw a nc bwe bw d zz 119-ball bga a selection guide 7c1347b-166 7c1347b-133 7c1347b-100 maximum access time (ns) 3.5 4.0 5.5 maximum operating current (ma) 420 375 325 maximum cmos standby current (ma) 10 10 10
cy7c1347b 4 pin definitions name i/o description a [16:0] input- synchronous address inputs used to select one of the 64k address locations. sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a [1:0] feed the 2-bit counter. bw [3:0] input- synchronous byte write select inputs, active low. qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low. when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw [3:0] and bwe ). bwe input- synchronous byte write enable input, active low. sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input-clock clock input. used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low. sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. adsp is ignored if ce 1 is high. ce 2 input- synchronous chip enable 2 input, active high. sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 input- synchronous chip enable 3 input, active low. sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, asynchronous input, active low. controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk. when asserted, it automatically incre- ments the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk. when asserted low, a [16:0] is captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk. when asserted low, a [16:0] is captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz ?sleep? input. this active high input places the device in a non-time-critical ?sleep? condition with data integrity preserved. for normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dq [31:0] dp [3:0] i/o- synchronous bidirectional data i/o lines. as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by a [16:0] during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dq [31:0] and dp [3:0] are placed in a three-state condition. v dd power supply power supply inputs to the core of the device. should be connected to 3.3v power supply. v ss ground ground for the core of the device. should be connected to ground of the system. v ddq i/o power supply power supply for the i/o circuitry. should be connected to a 3.3v or 2.5v power supply. v ssq i/o ground ground for the i/o circuitry. should be connected to ground of the system. mode input- static selects burst order. when tied to gnd selects linear burst sequence. when tied to v ddq or left floating selects interleaved burst sequence. this is a strap pin and should remain static during device operation. mode pin has an internal pull-up. nc no connects.
cy7c1347b 5 introduction functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t co ) is 3.5 ns (166-mhz device). the cy7c1347b supports secondary cache in systems utiliz- ing either a linear or interleaved burst sequence. the inter- leaved burst order supports pentium and i486 processors. the linear burst sequence is suited for processors that utilize a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the first ad- dress in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualified with the byte write enable (bwe ) and byte write select (bw [3:0] ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchro- nous self-timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank se- lection and output three-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are sat- isfied at clock rise: (1) adsp or adsc is asserted low, (2) ce 1 , ce 2 , ce 3 are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs (a [16:0] ) is stored into the address advancement logic and the address register while being presented to the memory core. the cor- responding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 3.5 ns (166-mhz device) if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. after the first cycle of the access, the outputs are controlled by the oe signal. consecutive single read cycles are supported. once the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output will three-state immediately. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clock rise: (1) adsp is asserted low, and (2) ce 1 , ce 2 , ce 3 are all asserted active. the address presented to a [16:0] is loaded into the address register and the address advancement logic while being delivered to the ram core. the write signals (gw , bwe , and bw [3:0] ) and adv inputs are ig- nored during this first cycle. adsp -triggered write accesses require two clock cycles to complete. if gw is asserted low on the second clock rise, the data presented to the dq [31:0] and dp [3:0] inputs is written into the corresponding address location in the ram core. if gw is high, then the write operation is controlled by bwe and bw [3:0] signals. the cy7c1347b provides byte write capabil- ity that is described in the write cycle description table. as- serting the byte write enable input (bwe ) with the selected byte write (bw [3:0] ) input will selectively write to only the de- sired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because the cy7c1347b is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq [31:0] and dp [3:0] inputs. doing so will three-state the output drivers. as a safety precaution, dq [31:0] and dp [3:0] are automatically three-stated whenever a write cycle is detected, regardless of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following condi- tions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) ce 1 , ce 2 , ce 3 are all asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw [3:0] ) are asserted active to conduct a write to the desired byte(s). adsc -triggered write accesses require a single clock cycle to complete. the address presented to a [16:0] is loaded into the address register and the address ad- vancement logic while being delivered to the ram core. the adv input is ignored during this cycle. if a global write is con- ducted, the data presented to the dq [31:0] and dp [3:0] is written into the corresponding address location in the ram core. if a byte write is conducted, only the selected bytes are written. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because the cy7c1347b is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq [31:0] and dp [3:0] inputs. doing so will three-state the output drivers. as a safety precaution, dq [31:0] and dp [3:0] are automatically three-stated whenever a write cycle is detected, regardless of the state of oe . burst sequences the cy7c1347b provides a two-bit wraparound counter, fed by a [1:0] , that implements either an interleaved or linear burst sequence. the interleaved burst sequence is designed specif- ically to support intel pentium applications. the linear burst sequence is designed to support processors that follow a lin- ear burst sequence. the burst sequence is user-selectable through the mode input. asserting adv low at clock rise will automatically increment the burst counter to the next address in the burst sequence. both read and write burst operations are supported.
cy7c1347b 6 sleep mode the zz input pin is an asynchronous input. asserting zz plac- es the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , ce 3 , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. . interleaved burst sequence first address second address third address fourth address a [1:0] a [1:0] a [1:0] a [1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst sequence first address second address third address fourth address a [1:0] a [1:0] a [1:0] a [1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz snooze mode standby current zz > v dd ? 0.2v 10 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns
cy7c1347b 7 cycle descriptions [1, 2, 3] next cycle add. used zz ce 3 ce 2 ce 1 adsp adsc adv oe dq write unselected none l x x 1 x 0 x x hi-z x unselected none l 1 x 0 0 x x x hi-z x unselected none l x 0 0 0 x x x hi-z x unselected none l 1 x 0 1 0 x x hi-z x unselected none l x 0 0 1 0 x x hi-z x begin readexternal l010 0 xxxhi-zx begin readexternal l010 1 0 xxhi-zread continue read next l x x x 1 1 0 1 hi-z read continue read next l x x x 1 1 0 0 dq read continue read next l x x 1 x 1 0 1 hi-z read continue read next l x x 1 x 1 0 0 dq read suspend read current l x x x 1 1 1 1 hi-z read suspend read current l x x x 1 1 1 0 dq read suspend read current l x x 1 x 1 1 1 hi-z read suspend read current l x x 1 x 1 1 0 dq read begin write current l x x x 1 1 1 x hi-z write begin write current l x x 1 x 1 1 x hi-z write begin writeexternal l010 1 0 xxhi-zwrite continue write next l x x x 1 1 0 x hi-z write continue write next l x x 1 x 1 0 x hi-z write suspend write current l x x x 1 1 1 x hi-z write suspend write current l x x 1 x 1 1 x hi-z write zz ?sleep? none hxxx x x xxhi-zx notes: 1. x = ?don't care,? 1 = high, 0 = low. 2. write is defined by bwe , bw [3:0] , and gw . see write cycle description table. 3. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock.
cy7c1347b 8 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ..................................... ? 65 c to +150 c ambient temperature with power applied .................................................. ? 55 c to +125 c supply voltage on v dd relative to gnd .........? 0.5v to +4.6v dc voltage applied to outputs in high z state [7] ....................................... ? 0.5v to v dd + 0.5v dc input voltage [7] .................................... ? 0.5v to v dd + 0.5v current into outputs (low)......................................... 20 ma static discharge voltage .......................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma notes: 4. x = ?don't care,? 1 = logic high, 0 = logic low. 5. the sram always initiates a read cycle when adsp asserted, regardless of the state of gw , bwe , or bw [3:0] . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to three-state. oe is a don't care for the remainder of the write cycle. 6. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle dq [31:0] ;dp [3:0] = high-z when oe is inactive or when the device is deselected, and dq [31:0] ;dp [3:0] = data when oe is active. 7. minimum voltage equals ? 2.0v for pulse durations of less than 20 ns. 8. t a is the case temperature. write cycle description [4, 5, 6] function gw bwe bw 3 bw 2 bw 1 bw 0 read 1 1xxxx read 101111 write byte 0 - dq [7:0] 101110 write byte 1 - dq [15:8] 101101 write bytes 1, 0 101100 write byte 2 - dq [23:16] 101011 write bytes 2, 0 101010 write bytes 2, 1 101001 write bytes 2, 1, 0 1 0 1 0 0 0 write byte 3 - dq [31:24] 100111 write bytes 3, 0 100110 write bytes 3, 1 100101 write bytes 3, 1, 0 1 0 0 1 0 0 write bytes 3, 2 100011 write bytes 3, 2, 0 1 0 0 0 1 0 write bytes 3, 2, 1 1 0 0 0 0 1 write all bytes 1 0 0 0 0 0 write all bytes 0 x x x x x operating range range ambient temperature [8] v dd v ddq com?l 0 c to +70 c 3.3v ? 5%/+10% 2.5v ? 5% 3.3v /+10% ind?l ?40 c to +85 c
cy7c1347b 9 electrical characteristics over the operating range parameter description test conditions min. max. unit v dd power supply voltage 3.3v ? 5%/+10% 3.135 3.6 v v ddq i/o supply voltage 2.5v ? 5% to 3.3v +10% 2.375 3.6 v v oh output high voltage v dd = min., i oh = ? 4.0 ma 2.4 v v ol output low voltage v dd = min., i ol = 8.0 ma 0.4 v v ih input high voltage 2.0 v dd + 0.3v v v il input low voltage [7] ?0.3 0.8 v i x input load current except zz and mode gnd v i v ddq ? 5 5 a input current of mode input = v ss ?30 a input = v ddq 5 a input current of zz input = v ss ?5 a input = v ddq 30 a i oz output leakage current gnd v i v ddq , output disabled ? 5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 6-ns cycle, 166 mhz 420 ma 7.5-ns cycle, 133 mhz 375 ma 10-ns cycle, 100 mhz 325 ma i sb1 automatic cs power-down current?ttl inputs max. v dd , device deselected, v in v ih or v in v il f = f max = 1/t cyc 6-ns cycle, 166 mhz 150 ma 7.5-ns cycle, 133 mhz 125 ma 10-ns cycle, 100 mhz 115 ma i sb2 automatic cs power-down current?cmos inputs max. v dd , device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speeds 10 ma i sb3 automatic cs power-down current?cmos inputs max. v dd , device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max = 1/t cyc 6-ns cycle, 166 mhz 120 ma 7.5-ns cycle, 133 mhz 95 ma 10-ns cycle, 100 mhz 85 ma i sb4 automatic cs power-down current?ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = 0 18 ma capacitance [9] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v. v ddq = 3.3v 6 pf c clk clock input capacitance 8 pf c i/o input/output capacitance 8 pf note: 9. tested initially and after any design or process changes that may affect these parameters.
cy7c1347b 10 ac test loads and waveforms output r=317 ? r=351 ? 5pf including jig and scope (a) (b) output r l =50 ? z 0 =50 ? v l = 1.5v 3.3v all input pulses [10] 2.5v gnd 90% 10% 90% 10% 2.5 ns 2.5 ns (c) switching characteristics over the operating range [11, 12, 13] -166 -133 -100 parameter description min. max. min. max. min. max. unit t cyc clock cycle time 6.0 7.5 10 ns t ch clock high 1.7 1.9 3.5 ns t cl clock low 1.7 1.9 3.5 ns t as address set-up before clk rise 1.5 1.5 1.5 ns t ah address hold after clk rise 0.5 0.5 0.5 ns t co data output valid after clk rise 3.5 4.0 5.5 ns t doh data output hold after clk rise 1.5 2.0 2.0 ns t ads adsp , adsc set-up before clk rise 1.5 1.5 1.5 ns t adh adsp , adsc hold after clk rise 0.5 0.5 0.5 ns t wes bwe , gw , bw [3:0] set-up before clk rise 1.5 1.5 1.5 ns t weh bwe , gw , bw [3:0] hold after clk rise 0.5 0.5 0.5 ns t advs adv set-up before clk rise 1.5 1.5 1.5 ns t advh adv hold after clk rise 0.5 0.5 0.5 ns t ds data input set-up before clk rise 1.5 1.5 1.5 ns t dh data input hold after clk rise 0.5 0.5 0.5 ns t ces chip select set-up 1.5 1.5 1.5 ns t ceh chip select hold after clk rise 0.5 0.5 0.5 ns t chz clock to high-z [12] 3.5 3.5 3.5 ns t clz clock to low-z [12] 0 0 0 ns t oehz oe high to output high-z [12, 13] 3.5 3.5 5.5 ns t oelz oe low to output low-z [12, 13] 0 0 0 ns t oev oe low to output valid [12] 3.5 4.0 5.5 ns notes: 10. input waveform should have a slew rate of 1 v/ns. 11. unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, inpu t pulse levels of 0 to 3.0v, and output loading of the specified i ol /i oh and load capacitance. shown in (a) and (b) of ac test loads. 12. t chz , t clz , t eov , t eolz , and t eohz are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 200 mv from steady-state voltage. 13. at any given voltage and temperature, t eohz is less than t eolz and t chz is less than t clz .
cy7c1347b 11 1 switching waveforms write cycle timing [14, 15] notes: 14. we is the combination of bwe , bw [3:0] , and gw to define a write cycle (see write cycle description table). 15. wdx stands for write data to address x. adsp clk adsc adv add ce 1 oe gw we ce 2 ce 3 1a data in t cyc t ch t cl t ads t adh t ads t adh t advs t advh wd1 wd2 wd3 t ah t as t ws t wh t wh t ws t ces t ceh t ces t ceh t ces t ceh 2b 3a 1a single write burst write unselected adsp ignored with ce 1 inactive ce 1 masks adsp = don?t care = undefined pipelined write 2a 2c 2d t dh t ds high-z high-z unselected with ce 2 adv must be inactive for adsp write adsc initiated write
cy7c1347b 12 read cycle timing [14, 16] note: 16. rdx stands for read data from address x. switching waveforms (continued) adsp clk adsc adv add ce 1 oe gw we ce 2 ce 3 2a 2c 1a data out t cyc t ch t cl t ads t adh t ads t adh t advs t advh rd1 rd2 rd3 t ah t as t ws t wh t wh t ws t ces t ceh t ces t ceh t ces t ceh t co t eov 2b 2c 2d 3a 1a t oehz t doh t clz t chz single read burst read unselected adsp ignored with ce 1 inactive suspend burst ce 1 masks adsp = don?t care = undefined pipelined read adsc initiated read unselected with ce 2
cy7c1347b 13 read/write cycle timing [14, 15, 16, 17] note: 17. data bus is driven by sram, but data is not guaranteed. switching waveforms (continued) adsp clk adsc adv add ce 1 oe gw we ce 2 ce 3 1a data in/out t cyc t ch t cl t ads t adh t ads t adh t advs t advh rd1 wd2 rd3 t ah t as t ws t wh t wh t ws t ces t ceh t ces t ceh t ces t ceh t eolz t co t eov 3a 3c 3d 1a t eohz t doh t chz single read burst read unselected adsp ignored with ce 1 inactive ce 1 masks adsp = don?t care = undefined pipelined read out 2a in 3b out out out out single write t ds t dh 2a out see note.
cy7c1347b 14 notes: 18. device originally deselected. 19. ce is the combination of ce 2 and ce 3 . all chip selects need to be active in order to select the device. switching waveforms (continued) t as = don?t care = undefined t clz t chz t doh clk add we ce 1 data in/out adsc adsp adv ce oe d(c) t cyc t ch t cl t ads t adh t ceh t ces t weh t wes t co pipeline timing [18, 19] adsp ignored with ce 1 high rd1 rd2 rd3 rd4 wd1 wd2 wd3 wd4 1a out 2a out 3a out 4a out 1a in 2a in 3a in 4a in back to back reads adsp initiated reads adsc initiated reads
cy7c1347b 15 switching waveforms (continued) adsp clk adsc ce 1 ce 3 low high zz t zzs t zzrec i dd i dd (active) three-state i/os notes: 20. device must be deselected when entering zz mode. see cycle descriptions table for all possible signal conditions to deselect the device. 21. i/os are in three-state when exiting zz sleep mode. zz mode timing [20, 21] ce 2 i ddzz high
cy7c1347b 16 document #: 38-00909-*d ordering information speed (mhz) ordering code package name package type operating range 166 cy7c1347b-166ac a101 100-lead thin quad flat pack commercial cy7c1347b-166bgc bg119 119-ball bga 133 CY7C1347B-133AC a101 100-lead thin quad flat pack cy7c1347b-133bgc bg119 119-ball bga cy7c1347b-133ai a101 100-lead thin quad flat pack industrial cy7c1347b-133bgi bg119 119-ball bga 100 cy7c1347b-100ac a101 100-lead thin quad flat pack commercial cy7c1347b-100bgc bg119 119-ball bga cy7c1347b-100ai a101 100-lead thin quad flat pack industrial cy7c1347b-100bgi bg119 119-ball bga package diagrams 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-a
cy7c1347b ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 119-lead fbga (14 x 22 x 2.4 mm) bg119 51-85115

▲Up To Search▲

Price & Availability of CY7C1347B-133AC

	To Download CY7C1347B-133AC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .